• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A pixel cell includes a first integrating capacitor, a second integrating capacitor, a photodetector, and a transistor. The first integration capacitor includes a first wire operatively coupled to the photodetector. The second integration capacitor includes a first wire. The transistor is operably coupled between the leads of the first and second integration capacitors to allow current to flow between the photodetector and the second integration capacitor only after a threshold voltage has been reached across the first capacitor. integration.
    公开号:BE1023008B1
    申请号:E2015/5204
    申请日:2015-04-01
    公开日:2016-11-03
    发明作者:Joshua Lund；Patrick Kuschak；Lin Minlong；Robert Brubaker
    申请人:Sensors Unlimited, Inc.；
    IPC主号:
    专利说明:

    INTEGRAL PIXELS AND METHODS PE OPERATION
    BACKGROUND OF THE INVENTION 1. DomamedePinvention
    The present invention relates to image sensor circuits and more particularly to pixel cells for, for example, a sensor array of an imager. 2. Description of related ar t
    Many imaging techniques use integral pixels that accumulate a photoelectric current produced in a photodetector, for example a photodiode, to charge an integrating capacitor. The amount of signal that the pixel can detect before saturation is called sink capacity and is proportional to the physical value of the integration capacitor. The sensitivity of an integrating pixel (or conversion gain) is also related to the capacitance value of the integration capacitor, mas is inversely proportional. In general, both high sensitivity and high sensitivity are desired. large capacity of. well, but these pixel performance parameters are typically in direct competition.
    With conventional embedded pixels, an attempt has been made to solve the problem by having several modes of operation, for example a mode for high sensitivity and a mode for large well capacity. In order to do this, a small integration capacitor is generally used for the high sensitivity mode and the switch connection of a larger, additional integration capacitor is enabled to activate the high capacity mode of the well. This switch is usually implemented by one or more transistors that operate on ON or OFF binary modes. In addition, sensor architectures are generally designed so that all the pixels of a matrix are homogeneously controlled, so that all the pixels operate only in high sensitivity mode or in high capacity mode.
    Conventional embedded pixels have limited imaging quality, due in part to the tradeoff between sensitivity and large well capacity. he
    There is a need in the art for integral pixels providing better imaging quality. The present invention provides a solution to this need. SUMMARY OF THE INVENTION A pixel cell comprises a first integrating capacitor, a second integrating capacitor, a photodetector, and a transistor. The first integration capacitor comprises a first wire operably coupled to the photodetector. The second integration capacitor comprises a first wire. The transistor is operably coupled between the wires of the first and second integration capacitors to permit current flow between the photodetector and the second integration capacitor only after a threshold voltage has been reached across the first capacitor of the transistor. integration.
    According to certain embodiments, the second integration capacitor has a capacity greater than that of the first integration capacitor. The pixel cell may also include a current mirror operatively coupled between the photodetector and the capacitors. The transistor may be an NOSM device and / or a PMOS type device. The pixel cell may also include a second transistor operably coupled between the photodetector and the first integrating capacitor. The photodetector may be a photodiode.
    The first and second integration capacitors may be operatively coupled in series or in parallel with the current path of a signal. The pixel cell may also include a voltage reset device and an input amplifier. The voltage reset device may be operably coupled to the first integration capacitor. The input amplifier may be operably coupled between the photodetector and a current mirror. Each of the first and second integration capacitors may be grounded and the current mirror may be operably coupled to bias voltage sources.
    A photoelectric current integration method for double gain pixel cells comprises receiving an electrical signal from a photodetector in a first integrating capacitor when the voltage of a first integrating capacitor is in a first voltage range, and receiving the electrical signal emitted by the photodetector into the first integrating capacitor and a second integrating capacitor when the voltage of the first integrating capacitor is in a second voltage range. The first voltage range is between a reset voltage and a threshold voltage. The pixel sensitivity and the sink capacity in the first voltage range are a function of the value of the first integration capacitor. The pixel sensitivity and the sink capacity in the second voltage range are a function of the sum of the values of the first and second integration capacitors. The first voltage range may be greater than the reset voltage. The second voltage range may be greater than or equal to the threshold voltage. The first voltage range may be less than a reset voltage. The second voltage range may be less than or equal to the threshold voltage.
    The foregoing features of the systems and methods of the present disclosure, and others, will become more apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments, in conjunction with that of the drawings.
    BRIEF DESCRIPTION OF THE DRAWINGS
    In order for the person skilled in the art to which this disclosure is readily to understand how to make and use the devices according to the present disclosure without carrying out unnecessary experiments, we will now describe in detail the preferred embodiments thereof by making reference to certain figures, in which: FIG. 1 is a schematic view of an exemplary embodiment of an integral pixel cell made according to the present invention, which shows the first and second integration capacitors arranged in series with respect to each other; to the current signal, with a current mirror operably coupled between a photodetector and the capacitors; Fig. 2 is a schematic view of an exemplary embodiment of an integral pixel cell made in accordance with the present invention which shows your first and second integration capacitors arranged in series with respect to the current signal; Fig. 3 is a schematic view of an exemplary embodiment of an integral pixel cell made in accordance with the present invention showing the first and second integration capacitors arranged in parallel with the current signal; and FIG. 4 is a curve of the integrated voltage as a function of the photoelectric current for the integral pixel cell of FIG.
    DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
    We will now refer to the drawings, in which the same reference numerals identify similar structural features or features of the present disclosure. For purposes of explanation and illustration, and not delimitation, a partial view of an exemplary embodiment of an integral pixel cell according to the disclosure is presented in FIG. 1 and generally designated by reference numeral 100. Other modes of Embodiments of integral pixel cells according to the disclosure, or aspects thereof, are shown in Figures 2 to 4, as will be described. The systems and methods described herein provide an integrating pixel having an operating mode such that each pixel of a matrix can operate in both high sensitivity and high power mode of I / O pulses. of the same exhibition.
    As shown in FIG. 1, a pixel cell 100 comprises a first integration capacitor 102, a second integration capacitor 104, a photodetector 106, for example a photodiode, and an NMOS transistor 108. The first integration capacitor 102 comprises a first lead 110 operatively coupled to collect a charge emanating from the photodetector 106. The second integration capacitor 104 comprises a first lead 112. The transistor 108 is operably coupled between the leads 110 and 112 of the first and second integration capacitors 102 and 104, respectively, to allow a photoelectric current to flow between the photodetector 106 and the second integration capacitor 104 only in the event that a threshold voltage V.sub.i has been reached on the prerraer-capacitor of the phototracker. 102. The second integration capacitor 104 has a capacity greater than that of the first integration capacitor 102.
    The threshold voltage Vseuii, as represented in FIG. 1, is governed by the following equation:
    wherein Vcoude is a voltage which represents the gate voltage of the transistor 108 and Vseuilnest a voltage which represents the NMOS threshold voltage of the transistor 108. Those skilled in the art will readily understand that it can adjust the threshold voltage Vseuii by adjusting the voltage Vcoude of transistor 108.
    Still with reference to FIG. 1, the first and second integration capacitors 102 and 104, respectively, are operatively coupled in series with respect to the current path of an electrical signal ISig. The pixel cell 100 includes a second PMOS transistor 120 operably coupled between the photodetector 106 and the first integration capacitor 102. The pixel cell 100 also includes a current mirror 118 operably coupled between the photodetector 106 and the capacitors 102 and 102. 104. The pixel cell 100 comprises an input amplifier 116. The input amplifier 116 is operably coupled between the photodetector 106 and the current mirror 118. MO and M1 of the current mirror 118 are operably coupled to sources respective polarizations 122 used to control the current mirror 118 and to synchronize a linear input photoelectric current and the mirror photoelectric current ISig. A voltage reset device 124 is operatively coupled to the first integration capacitor 102. The voltage reset device 124 has the function of resetting a voltage Vinti to the homes of the first integrating capacitor 102 to a resetting voltage Vremit . Each of the first and second integration capacitors 102 and 104, respectively, terminates in a ground network.
    The photodetector 106 produces an input photoelectric current Im. The second transistor 120 is coupled to the photodetector 106 and passes the photoelectric current Im emitted by the latter. The second transistor 120 is coupled to the current mirror 118. The current mirror 118 is designed to reproduce an electrical signal igig proportional to lin. The current mirror 118 is operatively coupled to the second integration capacitor 104 and the transistor 108. The transistor 408 controls the discharge of the first and second integration capacitors 102 and 104, respectively.
    The first and second integration capacitors 102 and 104 respectively have the function of converting the electrical signal ISig emitted by the photodetector 106 into a voltage, similar for example to the integrated voltage shown in FIG. 4 and described hereinafter. FIG. 1 shows the pixel cell 100 in low voltage high voltage integration, the curve of FIG. 4 representing a pixel cell 200 in high voltage low voltage integration. As will be readily understood by one skilled in the art, a curve representing the integrated voltage as a function of the photoelectric current for the pixel cell 100 would be identical to the curve illustrated in FIG. 4, except that the value of Vreinit would be greater than Vseuii.
    It is envisaged that during the initial exposure, equivalent for example to a voltage higher than Vseuü, when it is not necessary for the well capacity to be high, the transistor 108 allows the current to flow only from the first capacitor integration 102, for example the smallest integration capacitor. Under conditions where there is sufficient light for the electrical signal Lig to reach a threshold, equivalent for example to Vseuii in the first integration capacitor 102, the current flows from the first integration capacitor 102 and the second capacitor. 104, for example a larger integration capacitor, providing an individual pixel with both the high sensitivity of the first integration capacitor 102 and the high sink capacity of the second integration capacitor 104 during the same period of exposure. As will be understood by those skilled in the art, a low noise image at a high well capacity level is thus obtained, compared with an imager using conventional integral pixels. It can also improve! 'Irriageandrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
    As will be readily appreciated by those skilled in the art, the embodiments of the present invention provide for self-adjusting adaptive control to enable high well capacity in strong light and low well capacity - in low light this which can generate an extended dynamic range, which would be difficult to obtain otherwise by means of a single capacitor, small or large. Furthermore, as will also readily be understood by those skilled in the art, the pixel conversion gains of each pixel adapt independently when the level VSeuii is reached in each of the pixels, unlike conventional pixels where the mode is uniform for each pixel. the entire array of sensors. This tends to increase the dynamic range of the integrating pixel with respect to that of conventional integral pixels. In addition, although the pixel cells are described in connection with FIG. 1 as performing low voltage high voltage integration, it will be readily understood by those skilled in the art that the pixel cells can also perform low voltage high integration. voltage, as explained below with respect to Figure 2, Vseuü can for example be obtained in one direction or in selon other depending on whether the control transistor is an NMOS transistor or PMOS. Referring now to Figure 2, the pixel cell 200 is similar to the pixel cell 100. The pixel cell 200 includes a transistor 208 which is a PMOS transistor. The pixel cell 200 performs a high voltage low voltage integration, for example at a voltage less than V. The transistor 208 allows the current to flow only to a first integrating capacitor 202 and, from Vseuii and above, the Current flows to the first integration capacitor 202 and to a second integration capacitor 204. Those skilled in the art will readily appreciate that this provides similar benefits to those described above with respect to FIG. of pixels 200 does not have a current mirror, such as the current mirror 118, nor an input amplifier, such as the input amplifier 116. It will be readily understood by those skilled in the art that because of the absence current mirror, ISig is the same as that described above. It is contemplated that the current mirror and / or the amplifier have optional components. As will be readily understood by those skilled in the art, the pixel cell 200 may be used in a variety of suitable integration pixels.
    The threshold voltage Vseuii, as represented in FIG. 2, is governed by the following equation:
    wherein Vcoude is a voltage which represents the gate voltage of transistor 208 and Vseuiip is a voltage which represents the threshold voltage PMOS of transistor 208. Those skilled in the art will understand that he can adjust the threshold voltage Vseuii by adjusting the voltage VCOude of the transistor 208.
    As shown in Fig. 3, the pixel cell 300 is similar to the pixel cell 100. In the pixel cell 300, first and second integration capacitors 302 and 304, respectively, are arranged in parallel with the path current of the electrical signal ISig. Those skilled in the art will readily understand that the first and second integration capacitors 102 and 104 may be arranged either in series, as shown in FIG. 1, or in parallel as shown in FIG.
    Referring now to FIGS. 1-4, a photoelectric current integration procedure for double gain pixel cells, for example pixel cells 100, 200, and 300, includes receiving an electrical signal Isig in a premia. integration capacitor, for example the first integration capacitors 102, 202 and 302, when a voltage Vmti on the first integration capacitor is in a first voltage range, for example the first voltage range 401 The first voltage range is between the reset voltage Vreimt and the threshold voltage Vseuii. In the first voltage range, pixel sensitivity, for example a first conversion gain, and a first sink capacity are governed by the following equations:
    where CGI is the first conversion gain, WC1 is the first sink capacity and C1 is the value of the first integration capacitor.
    When Vinti is in a second voltage range, for example a second voltage range 403, an electrical signal ISig emitted by the photodetector is received in the first integrating capacitor and a second integrating capacitor, for example the capacitors d. integration 104, 204 and 304, resulting in an integrated voltage Vinti, 2 which is a function of both the first and second capacitor-integration. With regard to FIGS. 1 and 3, for example pixel cells 100 and 300, the second voltage range is less than or equal to Vseu.sub.i. With respect to FIGS. 2 and 4, for example the cell of pixels 200, the second voltage range is greater than or equal to the threshold voltage Vseu.sub.i. In the second voltage range, the pixel sensitivity, for example a second conversion gain, and a second sink capacity are governed by the following equations:
    where CG2 is the second conversion gain, WC2 is the second sink capacity, C1 is the value of the first integration capacitor, and C2 is the value of the second integration capacitor.
    According to the above equations, a voltage response of the pixel cell 200 is illustrated in FIG. 4. The voltage across the first integration capacitor 202 is reset at Vreinit, the integrated voltage therefore starts at Vreinit and as the current photoelectric, for example the electrical signal ISig, is present in time, the integrated voltage increases. Enter
    Vreinit and Vseuil; the integrated voltage and the current gain are a function of the first integration capacitor 202, the photoelectric charge for example accumulates "on the first integration capacitor 202. The voltage on the second integration capacitor 204 is reset to VCOude + Vseuiip, which is equal to Vseuil, as explained above. Therefore, when the integrated voltage reaches or exceeds Vseuii, the integrated voltage and the current gain are a function of both the first and second integrating capacitors 202 and 204, respectively, for example the progressive photoelectric charge will be encumbered on, both the first and the second integration capacitors 202 and 204, respectively. Those skilled in the art will readily understand that they can adjust Vseuii between the two conversion gains by setting Vcoude of the PMOS transistor 208 or by setting a PMOS threshold voltage Vseuiip of a PM OS transistor 220.
    The methods and systems of the present disclosure, as described above and illustrated in the drawings, provide optical sensing elements with superior properties, including improved image quality. The devices and methods of the present disclosure have been described and described with reference to preferred embodiments, but those skilled in the art will readily understand that they may make changes and / or modifications thereto without necessarily depart from the spirit and scope of this disclosure.
    权利要求:
    Claims (13)
    [1]
    A pixel cell comprising: a first integrating capacitor having a first wire operably coupled to a photodetector; a second integration capacitor having a first wire; and a transistor operably coupled between the wires of the first and second integration capacitors to permit current flow between the photodetector and the second integration capacitor only after a threshold voltage has been reached across the first capacitor of the capacitor. integration, the transistor being a single transistor having a first electrode which is a source / a drain and a second electrode which is a drain / a source, the first electrode being operably coupled to the photodetector and the first capacitor and the second electrode being functionally coupled to the second capacitor.
    [2]
    The pixel cell according to claim 1, wherein the second integrating capacitor has a capacitance greater than that of the first integrating capacitor,
    [3]
    The pixel cell of claim 1, further comprising a current mirror operably coupled between the photodetector and the capacitors.
    [4]
    The pixel cell according to claim 1, wherein the transistor is at least one of an NMOS type device or a PMOS type device.
    [5]
    The pixel cell of claim 1, further comprising a second transistor operably coupled between the photodetector and the first integrating capacitor.
    [6]
    The pixel cell of claim 1, wherein the photodetector is a photodiode. The pixel cell of claim 1, wherein the first and second integration capacitors are operably coupled in series with respect to the current path of a signal.
    [8]
    The pixel cell of claim 7, further comprising a voltage reset device operatively coupled to the first integrating capacitor and an input amplifier operably coupled between the photodetector and a current mirror, wherein each of the first and second integration capacitors are grounded, and wherein the current mirror is operably coupled to bias voltage sources. The pixel cell of claim 1, wherein the first and second integration capacitors are operably coupled in parallel with the current path of a signal.
    [10]
    A pixel cell according to claim 9, further comprising a voltage reset device operably coupled to the first integrating capacitor and an input amplifier operatively coupled between the photodetector and a current mirror, wherein each of the first and second integration capacitors are grounded, and wherein the current mirror is operably coupled to bias voltage sources.
    [11]
    A photoelectric current integrating method for double gain pixel cells, a cell comprising a first integrating capacitor having a first wire operably coupled to a photodetector; a second integration capacitor having a first wire; and a transistor operatively coupled between the wires of the first and second integration capacitors, the method comprising receiving an electrical signal output from the photodetector in the first integrating capacitor when the voltage of the first integrating capacitor is in a first voltage range, the first voltage range from a reset voltage to a threshold voltage, the pixel sensitivity and the well capacity in the first voltage range being a function of the value of the first integration capacitor; and receiving an electrical signal from the photo detector in the first integrating capacitor and the second integrating capacitor when the voltage of the first integrating capacitor is in a second voltage range, the sensitivity of the pixels and the well capacity in the second voltage range being a function of the sum of the values of the first and second integration capacitors.
    [12]
    The method of claim 11, wherein the first voltage range is greater than the reset voltage.
    [13]
    The method of claim 11, wherein the second voltage range is greater than or equal to the threshold voltage.
    [14]
    The method of claim 11, wherein the first voltage range is less than a reset voltage.
    [15]
    The method of claim 11, wherein the second voltage range is less than or equal to the threshold voltage.
    类似技术:
    公开号 | 公开日 | 专利标题
    BE1023008B1|2016-11-03|INTEGRAL PIXELS AND METHODS OF OPERATION
    BE1021668B1|2015-12-23|A PIXEL WITH A LARGE DYNAMIC RANGE AND A METHOD FOR OPERATING IT
    EP2912690B1|2019-12-25|Structure of a cmos active pixel
    EP3013037B1|2018-06-27|Pixel of image sensor having multiple detection node gains
    BE1021861B1|2016-01-22|PIXEL WITH DIRECT INJECTION IN BUFFER MEMORY FOR INFRARED DETECTOR ARRAYS
    FR2910710A1|2008-06-27|Image sensor controlling device for e.g. digital camera, has bias circuit including switch to connect source of transistor to charge voltage for increasing potential of source of transistor, when photodiode is discharged toward node
    EP1796373A1|2007-06-13|Imaging method with an image sensor with a high dynamic range
    FR3039928B1|2019-06-07|METHOD FOR CONTROLLING AN ACTIVE PIXEL IMAGE SENSOR
    EP2966687B1|2016-09-28|Cmos image sensor
    EP3324612B1|2020-01-29|Reduced noise cmos image sensor
    FR2924862A1|2009-06-12|PHOTOSENSITIVE MICROELECTRONIC DEVICE WITH AVALANCHE MULTIPLIERS
    BE1022761B1|2016-08-30|PERFORATED BLOCKING LAYER FOR IMPROVED BROADBAND ANSWERING IN A FOCAL PLAN NETWORK.
    FR3005205A1|2014-10-31|MULTI-CONVERSION GAIN IMAGE SENSOR
    EP2846357A1|2015-03-11|Photodetector device with semiconductor regions divided by a potential barrier
    EP3487167B1|2020-03-11|Image sensor with high dynamic range
    FR2962851A1|2012-01-20|IMAGE SENSOR
    FR3037440B1|2019-11-08|HIGH DYNAMIC IMAGE SENSOR WITH THREE-PART STORAGE NODE
    FR2945667A1|2010-11-19|INTEGRATED IMAGE SENSOR WITH VERY HIGH SENSITIVITY.
    FR3008826A1|2015-01-23|IMAGE SENSOR CELL WITH DUAL CONVERSION GAIN
    FR3096855A1|2020-12-04|Image sensor and its control method
    EP3026890B1|2019-06-05|Control of the integration time in a photosensitive device
    FR2992813A1|2014-01-03|METHOD FOR CONTROLLING A CMOS PIXEL
    EP3829160A1|2021-06-02|Pixel with adjustable dynamic range for noise reduction
    EP1146732B1|2009-10-21|Photosignal to voltage conversion device in image sensors with offset integrators
    EP3571834B1|2021-06-30|Adaptive generation of a high dynamic range image of a scene, on the basis of a plurality of images obtained by non-destructive reading of an image sensor
    同族专利:
    公开号 | 公开日
    IL237993D0|2015-11-30|
    US20150281612A1|2015-10-01|
    IL237993A|2018-05-31|
    US9686490B2|2017-06-20|
    BE1023008A1|2016-11-03|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20130194472A1|2012-02-01|2013-08-01|Sony Corporation|Solid-state imaging device, driving method and electronic device|
    US6246436B1|1997-11-03|2001-06-12|Agilent Technologies, Inc|Adjustable gain active pixel sensor|
    JP4502278B2|2004-02-27|2010-07-14|国立大学法人東北大学|Solid-state imaging device, line sensor, optical sensor, and operation method of solid-state imaging device|
    US7091531B2|2004-04-07|2006-08-15|Micron Technology, Inc.|High dynamic range pixel amplifier|
    US7825966B2|2007-06-29|2010-11-02|Omnivision Technologies, Inc.|High dynamic range sensor with blooming drain|
    US20140252239A1|2011-06-16|2014-09-11|Forstgarten International Holding Gmbh|Digital x-ray image sensor drive|
    US8970706B2|2011-09-22|2015-03-03|Basil Henry Scott|Dual pixel pitch imaging array with extended dynamic range|
    US9246023B2|2013-03-26|2016-01-26|Excelitas Canada, Inc.|Optical receiver with fast recovery time|
    US9136807B2|2013-07-16|2015-09-15|Analog Devices, Inc.|Apparatus and methods for electronic amplification|
    US9500752B2|2013-09-26|2016-11-22|Varian Medical Systems, Inc.|Pixel architecture for imaging devices|
    EP2890117B1|2013-12-26|2020-11-18|IMEC vzw|Improvements in or relating to imaging sensors|DE102016212784A1|2016-07-13|2018-01-18|Robert Bosch Gmbh|CMOS pixel, image sensor and camera and method for reading out a CMOS pixel|
    US10304522B2|2017-01-31|2019-05-28|International Business Machines Corporation|Method for low power operation and test using DRAM device|
    US9916890B1|2017-02-21|2018-03-13|International Business Machines Corporation|Predicting data correlation using multivalued logical outputs in static random access memorystorage cells|
    US10559213B2|2017-03-06|2020-02-11|Rosemount Aerospace Inc.|Method and system for aircraft taxi strike alerting|
    US10598710B2|2017-06-02|2020-03-24|International Business Machines Corporation|Cognitive analysis using applied analog circuits|
    US10037792B1|2017-06-02|2018-07-31|International Business Machines Corporation|Optimizing data approximation analysis using low power circuitry|
    US10663502B2|2017-06-02|2020-05-26|International Business Machines Corporation|Real time cognitive monitoring of correlations between variables|
    WO2019017908A1|2017-07-18|2019-01-24|Bae Systems Information And Electronic Systems Integration Inc.|Simultaneous multiple well size integration|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US14/242,597|2014-04-01|
    US14/242,597|US9686490B2|2014-04-01|2014-04-01|Integrating pixels and methods of operation|
    [返回顶部]